1. Field of the Invention
The present invention relates generally to a circuit with electrostatic discharge (ESD) protection for a switching regulator, and more particularly, to a circuit with ESD protection having lower on-resistance and high voltage conversion applied for the switching regulator.
2. Background
Electrostatic discharge (ESD) is an important issue for the design of the electronics devices, especially for the integrated circuits (ICs). The major source of ESD exposure to the ICs is from the human body, and is known as the Human Body Model (HBM) ESD source. A charge of about 0.6 C can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Any contact by a charged human body with a grounded object, such as the pin of an IC, can result in a discharge for about 100 ns with peak currents of several amperes to the IC. A second source of ESD is from the metallic objects, and is known as the machine model (MM) ESD source. The MM ESD source is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD model can result in ESD transients with significantly higher rise times than the HBM ESD source. A third ESD model is the charged device model (CDM). Unlike the HBM ESD source and the MM ESD source, the CDM ESD source includes situations where the IC itself becomes charged and discharges to ground. Thus, the ESD discharge current flows in the opposite direction in the IC than that of the HBM ESD source and the MM ESD source. CDM pulses also have very fast rise times compared to the HBM ESD source. A longstanding problem is that if such a high voltage is accidentally applied to the pins of an IC package, the discharge can cause gate oxide breakdown of the devices to which it is applied. The breakdown may cause immediate destruction of the device, or it may weaken the oxide enough such that failure may occur early in the operating life of the device and thereby cause later device failure in the field.
In particular, CMOS output circuits or combination input-and-output circuits use a combination of large NMOS and large PMOS transistors. These large transistors, the output transistors, are connected to the IC external terminals. The drains of the output transistors form the cathode or the anode of large diodes wherein the opposite diode terminal is connected to the respective well of each output transistor. The n type well for the PMOS transistor is connected to VDD, the positive or power supply potential in the IC. The p type well for the NMOS transistor is connected to the ground potential in the IC. In the most commercially prevalent CMOS, all p type wells are connected together through additional p type material which results in all n type wells individually forming diode connections with the one p type material at ground potential. Some ICs use ESD networks which add additional diodes in parallel to the diodes that are an integral part of the output transistors. This practice improves the diode connectivity between the IC external terminals and the power buses internal to the IC.
As shown in FIG. 1, it shows a conventional circuit with ESD protection in a switching regulator of the prior art. The signal transmitted by Lx pin of switch regulator is pulse shape waveform. For the efficiency consideration of the switch regulator, the Lx pin can not add an extra ESD protection circuit. Therefore, the tradition ESD solution of Lx for the switching regulator is to use the ESD rule layout, that is, to enlarge the distance between the drain terminal and gate terminal for power NMOS 3 and power PMOS 2 and to add extra an ESD protection cell 5. Such design increases higher on-resistance (Ron) to endure the pass of the ESD current through the power PMOS 2 to the ESD protection cell finally. Although the ESD rule layout for power NMOS 3 and power PMOS 2 can increase the on resistance (Ron) of power MOSs, it reduces the efficiency of the switch regulator. Namely, the conventional ESD design leads to trade-off between the ESD protection capability and the circuit efficiency.
U.S. Pat. No. 5,012,317, issued to Robert et al. entitled “Electrostatic discharge protection circuit” and U.S. Pat. No. 5,907,462, issued to Amitava et al. entitled “Electrostatic discharge protection circuit” and “Gate coupled SCR for ESD protection circuits” disclose similarly that changes in IC manufacturing technology often necessitate changes in the ESD protection scheme, generally because the process changes alter the ability of the ESD protection devices to operate. The silicide cladding of junctions and the incorporation of shallow trench isolation (STI) have been observed to reduce the gain of the parasitic bipolar device in the protection scheme, preventing proper triggering and conduction. The effects of these process changes are exacerbated by the continuing trend toward smaller device feature sizes, both laterally and vertically, rendering the devices ever more fragile to ESD.
However, the continued progression toward smaller device sizes has not, in many cases, relaxed the voltage requirements of the IC terminals. For example, a modern manufacturing process fabricates transistors having 0.18μ channel lengths, with a gate dielectric thickness of 7 nm or less, for use in ICs that must still tolerate operating voltages of up to 7 volts at input/output terminals. Many ICs are also required to have “failsafe” inputs and outputs, meaning that the terminal cannot be clamped to any power supply rail, so that large currents are not conducted from terminal voltages when the device is in an “off” state. The “failsafe” constraint is especially important in multi-voltage systems in which the inputs and outputs are power sequenced.
According above problems, the related filed need a circuit to overcome the disadvantage of the prior art.